1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a reference voltage generating circuit of a semiconductor memory apparatus.
2. Related Art
Generally, as shown in FIG. 1, a reference voltage generating circuit of a conventional semiconductor memory apparatus includes a driving unit 10 and a reference voltage generating unit 20.
The driving unit 10 supplies a predetermined voltage level to a voltage transfer node (VT_Node) in response to a power-up signal ‘Pwr’.
The reference voltage generating unit 20 generates a reference voltage Vref when the voltage level transferred to the voltage transfer node (VT_Node) is higher than a predetermined voltage level.
As shown in FIG. 2, the driving unit 10 includes first to third transistors P1, N1 and N2. The first transistor P1 has a gate that is connected to a ground voltage terminal VSS and a source to which an external power supply voltage VDD is applied from an external circuit. The second transistor N1 has a gate that is connected to a drain of the first transistor P1 and a source that is connected to the ground voltage terminal VSS. The third transistor N2 has a gate to which the power-up signal ‘Pwr’ is applied, a drain that is connected to the drain of the first transistor P1, and a source that is connected to the voltage transfer node (VT_Node).
If the external power supply voltage VDD is applied to the semiconductor memory apparatus, then the power-up signal ‘Pwr’ transitions to the voltage level of the external power supply voltage VDD and then transitions to the voltage level of the ground voltage VSS after a predetermined time.
The operation of the reference voltage generating circuit of the conventional semiconductor memory apparatus will be described below.
The gate of the first transistor P1 is tied to ground. Thus, it is always on and when the external power supply voltage VDD is applied to the source of the first transistor P1, then the voltage of node (S1) will be raised to a voltage level close to the supply voltage VDD.
The voltage on node (S1) will then be applied to the gate and the drain of the second transistor N1, turning the second transistor N1 on and establishing a constant voltage level on node (S1). At the same time, the third transistor N2 is turned on because the power-up signal ‘Pwr’ transitions to a level close to or the same as the external power supply voltage VDD, when the external power supply voltage VDD is applied.
The third transistor N2 transfers the voltage that is generated at node S1 to the voltage transfer node (VT_Node), where the first transistor P1 is connected to the second transistor N1.
Therefore, when the power-up signal ‘Pwr’ has a voltage level close to that of the external power supply voltage VDD, then the constant voltage level generated at node (S1) is applied to the voltage transfer node (VT_Node).
The reference voltage generating unit 20 generates the reference voltage Vref when a voltage level at the voltage transfer node VT_Node is higher than a predetermined voltage level.
Generally, the turn on voltage, i.e., the gate-source voltage of a transistor increases as the temperature goes down. Accordingly, as the temperature goes down, the gate-source voltage has to increase in order for the transistor to turn on.
However, in the third transistor N2 of the driving unit 10, the voltage level of the power-up signal ‘Pwr’, which is applied to the gate, may not be sufficient to turn on the third transistor N2 as the temperature goes down, because the voltage level of the power-up signal ‘Pwr’ does not vary with the temperature. Accordingly, the driving unit 10 may not be able to supply a sufficient voltage to the voltage transfer node (VT_Node) to cause the reference voltage generating unit to generate the reference voltage (Vref).